1. Field of the Invention
The present invention relates to a three-dimensional multichip module (MCM) and a semiconductor chip which can be used in this MCM. More particularly, the present invention relates to a technique for designing and manufacturing a semiconductor chip, such as a standard cell and an embedded array which can be used in an MCM, using computer-aided design (CAD). Further, the present invention relates to a storage medium for storing data used when design using CAD is carried out.
2. Description of the Related Art
Gate array, standard cell and embedded array are conventionally known methods for efficiently designing a semicustom LSI, as means for designing an Application Specific Integrated circuit (ASIC), which simply realizes a device for specific application using CAD.
A gate array is formed by preparing a master wafer beforehand, having transistors laid thereon in an array, and adding interconnections to the master wafer so as to produce a logic system. As shown in the example of FIG. 1, bonding pads (I/O pads) 101 are provided at the peripheral region of a chip, and a random logic block 102 is provided in the remaining region (central region) of the chip. In the random logic block 102, transistors are laid in an array.
However, a gate array architecture cannot be used to realize a large-scale macrocell such as a CPU or a memory. For this reason, a standard cell design methodology was introduced to simply realize a large-scale macrocell. To produce a standard cell, optimally designed and verified macrocells, registered beforehand in a CAD design database, are assembled in a predetermined layout using CAD. As shown in the example of FIG. 2, bonding pads 201 are provided at the peripheral region of the chip, and macrocells, comprising a CPU core 202, a RAM 203, a RAMBUS interface 204, a PLL 205 and a ROM 206, are provided in central region of the chip. These macrocells are directly connected to each other by interconnections.
The standard cell architecture enables large-scale macrocells to be formed easily, but has a disadvantage that the fabrication of each macrocell must start from the transistor unit level, or from the beginning of the fabrication process, lengthening development time.
Therefore, an embedded array architecture, in which standard cell macrocells are buried in the random logic block of a gate array, has been proposed.
This embedded array is manufactured after the number of gates and the types of macrocells to be contained within the random logic block have been decided. In other words, the embedded array is customised after the wafer process has been commenced but prior to the metallization process. In this state, completion of the logic design is awaited and, after a logic simulation has been carried out, the embedded array is completed by providing interconnections to the random logic block. As shown in the example of FIG. 3, bonding pads 301 are provided at the peripheral region of the chip, and macrocells comprising a CPU core 302, a RAM 303, a RAMBUS interface 304, a PLL 305 and a ROM 306, are provided in central region of the chip. In addition, a random logic block 307 is provided in order to realize the functions of these macrocells.
This embedded array comprises the random logic block, and therefore the customization of the embedded array do not need to be started from the transistor unit level. Consequently, time needed to develop the standard cell can be reduced. Moreover, changes to the circuits of the random logic block can dealt with simply by changing the interconnections.
However, on the conventional embedded array or the standard cell, no bump pads are prepared as the components of the cells for connecting to another chip directly above or below the embedded array or the standard cell. Then, when assembling an MCM with a chip fabricated by the conventional embedded array or the standard cell approach in combination with another pre-existing chip, these chips must be disposed in a side-by-side configuration, or two-dimensional configuration as shown in FIG. 4A and FIG. 4B.
FIG. 4A is a top view, and FIG. 4B, a side view. As shown in FIG. 4A and FIG. 4B, a chip 401 and a chip 402 are provided on a lead frame 400. Chip 401 is the conventional embedded array or the standard cell, and chip 402 is the pre-existing chip. Since it is not possible to stack the chips 401 and 402 three-dimensionally one above the other, they are arranged side by side on the lead frame 400. Then the right side bonding pads 403 on chip 401, and the left side bonding pads 404 on chip 402 are connected by bonding wires 407. And the left side bonding pads 403 on chip 401 and leads 406 are connected by bonding wires 405. Further, the right side bonding pads 404 on the chip 402 and leads 409 are connected by bonding wires 408.
The above structure, wherein multiple chips are two-dimensionally provided side by side, makes it impossible to reduce the area of the frame to less than the total area of the chips. As a result, the mounting area of the package cannot be made small.
Furthermore, the conventional MCM has a problem that electrical signals exchanged between the chips are delayed due to the long distance of the interconnections between the chips. As a consequence, it has been difficult to achieve high-speed executions with the conventional MCM. Furthermore, in a two-dimensional chip structure, it has been difficult to reduce noise generated by electrical signals exchanged between the chips.